Emacs, scripting and anything text oriented.

SystemVerilog

Kaushal Modi

Arbitrary SystemVerilog snippets

Queues and Arrays #

Associative Arrays #

Section 7.8 Associative arrays from SystemVerilog standard IEEE 1800-2017

typedef enum {SOURCE_REF, SOURCE_AUX, SOURCE_NCO, SOURCE_UTS, SOURCE_FBK} kind_t;

//  +--------------------+--> For assoc array element «KEY: VAL», VAL is a queue ($) of type "int"
//  |                    |
// int kind_map [kind_t][$] =
//     ^         ^
//     |         |
//     |         +-- For assoc array element «KEY: VAL», KEY is of type "kind_t"
//     |
//     +-- Variable name of the assoc array

int kind_map [kind_t][$] = '{
                             SOURCE_REF: '{1, 2, 3},
                             SOURCE_AUX: '{2, 3, 4},
                             SOURCE_NCO: '{3, 4, 5},
                             SOURCE_UTS: '{4, 5, 6},
                             SOURCE_FBK: '{5, 6, 7}
                             };

initial begin
  $display("%0d entries", kind_map.num);
  $display("kind_map = %p", kind_map);
  foreach (kind_map[i]) begin
    $display("kind_map[%p] = %p", i, kind_map[i]);
    $display("  key = %p (type = %s)", i, $typename(i));
    $display("  value = %p (type = %s)", kind_map[i], $typename(kind_map[i]));
  end
end
Code Snippet 1: Associative arrays where index values are queues

Introspection #

Printing type/class of a variable/object #

Section 20.6.1 Type name function from SystemVerilog standard IEEE 1800-2017

See the use of $typename in Code Snippet 1.

Types #

Enums #

Number of enum elements #

Section 6.19.5.5 Num() from SystemVerilog standard IEEE 1800-2017

typedef enum {SOURCE_REF, SOURCE_AUX, SOURCE_NCO, SOURCE_UTS, SOURCE_FBK} kind_t;

kind_t foo;

initial begin
  $display("number of elements in kind_t: %0d", foo.num());
end

Loop through all enum values #

typedef enum {SOURCE_REF, SOURCE_AUX, SOURCE_NCO, SOURCE_UTS, SOURCE_FBK} kind_t;

kind_t foo;

initial begin
  foo = foo.first();
  while (1) begin
    $display("foo = %s", foo.name());
    if (foo == foo.last()) break;
    else foo = foo.next();
  end
end

Template #

`timescale 1ns/1ps

module top;

  // <custom code here>

  // Sim duration
  initial begin
    #400ns;
    $finish;
  end

  // timeformat and wave config
  initial begin
    $timeformat(-9, 3, "ns");  // units, precision, suffix
    $shm_open("waves.shm");
    $shm_probe("ACTM");
  end

endmodule: top

Versions used: systemverilog IEEE 1800-2017 , xcelium 18.03-s006

If you have written a response to this, enter your response post's URL below.

Or, you can send a "comment" webmention (it's OK if you don't know what that means). When asked about your website on an IndieAuth login screen, simply type https://commentpara.de.

Markdown Support**bold**, _italics_, ~~strikethrough~~, [descr](link), `monospace`, ```LANG\nline1\nline2\n``` (Yep, multi-line code blocks too, with syntax highlighting!), auto-hyperlinking.

Webmentions #